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smsc ds ? usb97cfdc2-01 rev. 02-27-07 datasheet usb97cfdc2-01 usb floppy disk controller features ? 3.3 volt, low power operation ? complete usb specific ation 1.1 compatibility - includes usb transceiver - based on an enhanced version of smsc?s industry proven usb97c100 usb controller ? complete system solution including usb mass storage class compliant win98/2000 driver and firmware - supports 640k, 720k, 1.44m, 1.2m windows 98 j, and 1.2m nec dos 6.x formats - supports both the ufi and sff8070i command sets - supports usb mass storage compliant bootable floppy bios - 4ms seek times - usb 1.1 compliance, including low power device class suspend mode operation and power control of disk drive - disk drive feedback of readiness upon power re-application option - option for ultra high performance using additional caching sram - support for floppy drive power control ? contains smsc?s industry proven floppy disk controller - licensed cmos 765b floppy disk controller - supports single normal or three mode floppy drives - supports vertical recording format and high capacity drives in user written firmware applications - detects all overrun and underrun conditions - sophisticated power control circuitry (pcc) including multiple powerdown modes for reduced power consumption ? enhanced digital data separator - 1 mbps, 500 kbps, 300 kbps, 250 kbps data rates - programmable precompensation modes ? intelligent auto power management - <250a suspend current - <75ma operating current ? integrated 32kbyte program rom - uses external 3 wire serial eeprom provides storage for unique oem i dentification and string descriptors and drive option settings. - 10 options for various drive parameters are externally selectable via serial eeprom data. ? optional external program memory interface for custom applications - 32k byte code space - flash, sram, or eprom memory ? 4kb internal buffer sr am for high performance operation ? integrated 14.318 mhz cr ystal driver circuit ? 100 pin tqfp lead-free rohs compliant package (12.0 x 12.0 mm body) - 25% smaller body size than other 100 pin tqfp packages ordering information order number: USB97CFDC2-MV-01x for 100 pin tqfp lead-free rohs compliant package
smsc ds ? usb97cfdc2-01 page 2 rev. 02-27-07 datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2007 smsc or its subs idiaries. all rights reserved. circuit diagrams and other information rela ting to smsc products are included as a m eans of illustrating typical applications. consequently, complete information sufficient for construction pur poses is not necessarily given. although the informat ion has been checked and is bel ieved to be accurate, no responsibility is assumed for ina ccuracies. smsc reserves the ri ght to make changes to specif ications and product descriptions at any time without notice. contact your local smsc sales office to obtain the late st specifications bef ore placing your product order. the provisi on of this information does not convey to the purchas er of the described semiconducto r devices any licenses under any patent rights or other intellect ual property rights of smsc or others. all sales are expressly conditional on your agr eement to the terms and conditions of the most re cently dated ve rsion of smsc's standard terms of sale agreement dated before the date of y our order (the "terms of sale ag reement"). the product may contain d esign defects or errors known as anomalies which may cause the product's f unctions to deviate from published s pecifications. a nomaly sheets are available upon request. smsc products are not des igned, intended, authorized or wa rranted for use in any life s upport or other application whe re product failure could cause or contri bute to personal injury or severe property damage. an y and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc litera ture, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at http:// www.smsc.com. smsc is a registered tr ademark of standard microsystems corporation (?smsc?). product names and company names are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantability, fitness for a particular purpose, ti tle, and against infringement and the like, and any and all warranties arising from any course of dealing or usag e of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, p unitive, or consequential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contract; tort; negligence of smsc or others; strict liability; breach of warranty; or othe rwise; whether or not any remedy of buyer is held to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
smsc ds ? usb97cfdc2-01 page 3 rev. 02-27-07 datasheet 1 general description the usb97cfdc2-01 is an integration of an enhanced multi-endpoint usb 1.1 peripheral controller, a 32k byte program rom, and the smsc floppy di sk controller used in many of it s super io products, such as the fdc37c869. special care in the design has been taken to a ssure the lowest possible system current draw (<250a) during suspend mode operation. provisions for external program flash memory up to 32k bytes for program storage is provided for customized applications. several pins are provided for controlling external power control elements and sensing specialized drive functions. individual manufacturers may provide their unique usb v endor and product ids and descriptor strings via an external 3 wire serial eeprom. up to 16 different configuration opti ons for various drive related parameters are provided by 4 external configuration input pins which can be read at power-on reset.
smsc ds ? usb97cfdc2-01 page 4 rev. 02-27-07 datasheet table of contents 1 general des cription ............................................................................................................ .................3 2 description of pin functions ................................................................................................... ........5 3 pin configuration.............................................................................................................. .....................6 4 block diagram .................................................................................................................. ........................7 5 pin descriptions............................................................................................................... .........................8 5.1 b uffer t ype d escriptions ....................................................................................................................11 6 configuration options.......................................................................................................... ............12 7 board test mode operation ...................................................................................................... .....14 8 dc parameters.................................................................................................................. .......................15 9 ac parameters.................................................................................................................. .......................17 10 usb parameters................................................................................................................. ......................19 10.1 usb dc parameters..................................................................................................................... ....19 10.2 usb ac parameters..................................................................................................................... ....21 11 mechanical outline ............................................................................................................. ...............24
smsc ds ? usb97cfdc2-01 page 5 rev. 02-27-07 datasheet 2 description of pin functions floppy disk interface (14 pins) ntrk0 nindex nwrtprt ndskchg nrdata drvden0 drvden1 nstep nwdata nwgate nhdsel ndir ndso nmtr0 usb interface (4 pins) usb+ usb- avdd agnd external flash rom interface (26 pins) fd0/opt0 fd1/opt1 fd2/opt2 fd3/opt3 fd4/in0 fd5/out0 fd 6/out1 fd7/out2 fa0 fa1 fa2 fa3 fa4 fa5 fa6 fa7 fa8 fa9 fa10 fa11 fa12 fa13 fa14 fa15 nfrd nfce misc (10 pins) romen hdo ndrvrdy nfdpwr xtal1/clkin xtal2 nreset ntest tst_out ntesten power, grounds, and no connects (46 pins)
smsc ds ? usb97cfdc2-01 page 6 rev. 02-27-07 datasheet 3 pin configuration n.c. n.c. n.c. n.c. n.c. n.c. n.c. gnd n.c. n.c. n.c. n.c. n.c. vdd ntest vdd xtal1/clkin xtal2 gnd romen nreset tstout n.c. hdo ndrvrdy usb97cfdc2 1 25 51 75 nrdata nwrtprt ntrk0 nindex nhdsel nwgate nwdata nstep ndir gnd nds0 nmtr0 drvden0 agnd usb+ vdd usb- avdd fa11 fa9 fa8 fa13 fa14 gnd n.c. ndskchg drvden1 n.c. gnd n.c. gnd vdd n.c. n.c. n.c. n.c. n.c. gnd n.c. n.c. n.c. n.c. vdd n.c. n.c. n.c. n.c. n.c. n.c. n.c. fa15 fa12 fa7 fa6 fa5 fa4 fa3 gnd fa2 fa1 fa0 vdd fd0/opt0 fd1/opt1 fd2/opt2 fd3/opt3 fd4/in0 fd5/out0 fd6/out1 fd7/out2 nfce fa10 nfrd gnd nfdpwr usb97cfdc2-01
smsc ds ? usb97cfdc2-01 page 7 rev. 02-27-07 datasheet 4 block diagram 8051 cpu 8237 4k data buffer ram memory management unit map ram arbiter sie dma rx/tx queue end point control serial interface engine gpio fd[7:0]/opt[3:0] /in0/out[2:0] nfrd nfce drive control flash/ sram interface irq0 sd[7:0] sa[13:0] niow nior nmemw nmemr high speed usb xcvr to usb bus fa[15:0] floppy disk controller drq2 tc ndak2 address decode nce aen sram interface ntrk0, nindex, nwrtprt, ndskchg nrdata, drvden0, drvden1, nwdata, nwgate, nhdsel, ndir, nmtr0, nds0, nstep drive interface clock control nhdo ndrvrdy nfdpwr 32k byte program rom romen
smsc ds ? usb97cfdc2-01 page 8 rev. 02-27-07 datasheet 5 pin descriptions pin no. name symbol buffer type description floppy disk interface 75 read disk data nrdata is raw serial bit stream from the disk drive, low active. each falling edge represents a flux transition of the encoded data. 69 write data nwdata od12 this active low hi gh current driver provides the encoded data to the disk drive. each falling edge causes a flux transition on the media. this pin is high impedance when nreset is active low. 71 head select nhdsel od12 this high current output selects the floppy disk side for reading or writing. a logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. . this pin is high impedance when nreset is active low. 67 direction control ndir od12 this high current lo w active output determines the direction of the head movement. a logic "1" on this pin means outward motion, while a logic "0" means inward motion. this pin is high impedance when nreset is active low. 68 step pulse nstep od12 this active lo w high current driver issues a low pulse for each track-to-track movement of the head. this pin is high impedance when nreset is active low. 76 disk change ndskchg is this input s enses that the dr ive door is open or that the diskette has possibly been changed since the last drive selection. 63 drvden 0 drvden 0 od12 an active low on this pin indicates a disk drive spindle speed change from 300 rpm to 360 rpm or 1.2m format disks in three mode drives. this pin should be tied to the disk drives spindle speed control input pin. this pin is high impedance when nreset is active low. 77 drvden 1 drvden1 od12 reserved for future use. 70 write gate nwgate od12 this active lo w high current driver allows current to flow through the write head. it becomes active just prior to writing to the diskette. this pin is high impedance when nreset is active low. 73 track 0 ntrk0 is this active low schmitt trigger input senses from the disk drive that the head is positioned over the outermost track. 72 index nindex is this active low schmitt trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. 74 write protect nwrtprt is this active low schmitt trigger input senses from the disk drive that a disk is write protected. any write command is ignored. 64 motor on 0 nmtr0 od12 this active low open drain output selects motor drive 0. this pin is high impedance when nreset is active low. 65 drive select 0 nds0 od12 this active low open drain output selects drive 0. this pin is high impedance when nreset is active low.
smsc ds ? usb97cfdc2-01 page 9 rev. 02-27-07 datasheet pin no. name symbol buffer type description usb interface 59 61 usb bus data usb- usb+ io-u these pins connect to the usb data signals through 33 ohm series resistors. the usb+ line should be pulled up with a 5%, 1.5k ohm resistor to indicate that this is a high speed usb device. 58 usb transceiver supply avdd this is the 3.3v supply to the internal usb transceiver. 62 usb transceiver ground agnd this is the supply ground for the internal usb transceiver. program memory interface 38-35 program memory data bus/option select fd[3:0]/ opt[3:0] io8 these signals are used to transfer data between the internal 8051 and the external program memory when operating in external program memory mode (see romen pin). when operating from internal program memory, the opt3 pin must be tied high thru a resistor and the opt[2:0] pins tied low thru a resistor (see configuration description section). these pins are not driven while the usb97cfdc2-01 is in suspend mode and internal rom mode is active. they are driven while in suspend in external rom mode.. 34 program memory data bus/eeprom input fd4/in0 io8 this signal is used to transfer data between the internal 8051 and the external program memory when operating in external program memory mode (see romen pin). when operating from internal program memory, this pin is the input data from an external serial eeprom that contains manufacturer specific id and string information, as required by the usb s pecification, and drive options. this pin is not driven while the usb97cfdc2-01 is in suspend mode and internal rom mode is active. it is driven while in suspend in external rom mode... 33-31 program memory data bus/eeprom output fd[7:5]/ out[2:0] io8 this signal is used to transfer data between the internal 8051 and the external program memory when operating in external program memory mode (see romen pin). when operating from internal program memory, these pi ns are the output data and strobes to an external serial eeprom that contains manufacturer specific id and string information, as required by the usb specification, and drive options. these pi ns are driven while the usb97cfdc2-01 is in suspend mode. 50, 53, 54, 49, 57, 29, 56, 55, 48- 44, 42-40, flash memory address bus fa[15:0] o8 these signals address memory locations within the flash memory. 28 flash memory read strobe nfrd o8 flash rom read; active low 30 flash memory chip select nfce o8 flash rom chip select; active low miscellaneous 17 crystal input/external clock input xtal1/ clkin iclkx 14.318mhz crystal or clock input. this pin can be connected to one terminal of the crystal or can be connected to an external 14.318mhz clock when a crystal is not used.
smsc ds ? usb97cfdc2-01 page 10 rev. 02-27-07 datasheet pin no. name symbol buffer type description 18 crystal output xtal2 oclkx 14.318mhz crystal this is the other terminal of the crystal, or left open when an external clock source is used to drive xtal1/clkin. it may not be used to drive any external circuitry other than the crystal circuit. 20 rom enable romen ip if this input is tied high or left open, the internal program rom is enabled. if tied low, external program memory can be used for custom applications. 24 drive density output hdo i in some configurations of the usb97cfdc, this drive pin indicates if a 640/720k disk is inserted in the drive. polarity of this signal is determined by the configuration selected by the opt[3:0] pins at reset. if this pin is not driv en by the drive, it should be tied low. 25 drive ready ndrvrdy i an active low signal on this pin from the floppy disk drive, after ds0 goes active, indicates that the system may activate mtr0. if the drive does not supply this signal, this pin should be tied low. 26 drive power nfdpwr od24 this active low signal is intended to activate an external power switch, eit her in the drive or on the system board, to supply power to the floppy disk drive. it is active whenever the usb97cfdc2-01 is not in suspend mode. 21 reset input nreset is this active low signal is used by the system to reset the chip. the active low pulse should be at least 100ns wide. 22 test output tstout o8 this signal is used for testing the chip via an internal xnor chain. user should normally leave it unconnected. 15 test input ntest i this signal is a manufacturing test pin. it should be tied to vdd for normal operation. 16 test enable ntesten i this active low signal places the device into board test mode using the xnor chain. for normal operation this pin should be tied high. see board test mode operation on page 14 power, ground, and no connects 14, 39, 60, 82, 93 vdd +3.3v power 8, 19, 27, 43, 52, 66, 79, 81, 88 gnd ground reference 1-7, 9-13, 23, 51, 78, 80, 83-87, 89-92, 94-100 nc no connect. these pins should not be connected externally.
smsc ds ? usb97cfdc2-01 page 11 rev. 02-27-07 datasheet 5.1 buffer type descriptions table 1 - usb97cfdc2-01 buffer type descriptions buffer description i input ip input with 30ua pull-up is input with schmitt trigger o8 output with 8ma drive io8 input/output with 8ma drive io8p input/output with 8ma drive and 30ua pull-up od12 open drain?.12ma sink o24 output with 24ma drive od24 open drain?.24ma sink iclkx xtal clock input oclkx xtal clock output i/o-u see table 6.
smsc ds ? usb97cfdc2-01 page 12 rev. 02-27-07 datasheet 6 configuration options if romen is tied high, then the internal rom code is used for operation. if low, then an external memory on the fd bus is used for operational code. if the internal rom is used, opt3 must be tied high and opt[ 2:0] must be tied low through a resistor. in this mode, an external serial eeprom is used to store the oem?s usb assigned vid, their pid, their product string, and the options for the particular drive connected to the usb97cfdc2-01. the data in the eeprom is organized as follows: note: if the data is not of the specif ied length, then fill t he length with zeros, following the data. device descriptor - 18 bytes for a device with a vid/pid of 0424/0dc, the device descriptor looks lik e the one below. (note that the data is separated by carriage returns in the ?eeprom.dat? file. it is displayed here on a single line for clarity?s sake.) the vid/pid occupy byte position 9 through 12. 12 0110 01 00 00 00 40 24 04 dc 0f 22 01 01 02 00 01 the data in bold are the vid and pid in formation. note that the lo and the hi bytes are swapped, as in vendorlo, vendorhi, productlo and producthi. language string - 4 bytes string: 0409 (the language code for english) eeprom.dat: 04 03 09 04 (1 st byte is the length, then the string id, followed by the language id in little endian.) manufacturer string ? 60 bytes (unicode format) example string: smsc eeprom.dat: 3c 03 53 00 4d 00 53 00 43 00 ? 00 (1 st byte is the length, followed by the string id and the unicode string itself in little endian.) product string ? 60 by tes (unicode format) example string: usb fdc eeprom.dat: 3c 03 55 00 53 00 42 00 20 00 46 00 44 00 43 00 ? 00 (again the 1 st byte is the length, followed by the string id and the unicode st ring itself in little endian.) serial number string ? 60 bytes (unicode format) string: none eeprom.dat: 3c 03 4e 00 6f 00 6e 00 65 00 ? 00 (again the 1 st byte is the length, follo wed by the string id and the unicode string itself in little endian.) inquiry data (in response to a ufi_inquiry request) - 36 bytes bytes 0 ? 7: the values for the 1 st 8 bytes of the inquiry data come fr om table 10 of the usb mass storage class ufi command specification. for the usb floppy device, those bytes should be 00 80 00 01 1f 00 00 00. these bytes do not change. bytes 8 ? 15: vendor information (example: smsc) eeprom.dat: 53 4d 53 43 20 bytes 16 ? 31: product identification (example: usb fdd) eeprom.dat: 55 53 42 20 46 44 44 20 bytes 32 ? 35: product revision level (example: 2.00) eeprom.dat: 32 2e 30 30
smsc ds ? usb97cfdc2-01 page 13 rev. 02-27-07 datasheet attributes ? 4 bytes (obtained from section 3.0) example: the value for your drive from tabl e 3- attributes for the variants is ?0005 0000? eeprom.dat: 00 05 00 00 attributes tape bits hdo pin high drvrdy delay dskchg detect 0014 0000 not set 2hd before motor on motor on c014 0004 set 2dd before motor on motor on 0005 0000 not set 2dd before motor on motor on 0001 0000 not set n/a before motor on motor on 0087 0000 not set 2dd n/a motor on 8004 0002 set 2dd before motor on motor on 000c 0000 not set 2hd after motor on motor on 020c 0000 not set 2hd after motor on motor off 802c 0000 set 2hd after motor on motor on 33ac 0000 set 2hd after motor on motor on 0005 0001 not set 2hd before motor on motor on 0405 0001 not set 2hd before motor on motor off notes: 1. the tape bits being set place the fdc controller?s dat a clock separator into a mode which has more spindle speed variation tolerance (for small form factor drives) but slightly less bit jitter tolerance. 2. if the hdo pin is not provided use variant 0001 0000. 3. the drvrdy delay refers to either delaying the motor on command until drvrdy goes active after power up (?before motor on?) or waiting after the motoro on command is given to the dr ive until drvrdy is active before issuing a step command to the drive (?after motor on ?). this applies only to drives with a drvrdy pin. for those that do not, the drvrdy i nput should be tied high (active) so that this delay is not used. 4. the dskchg colum refers to whether the drive r equires its motor to be on befor e it will update the dskchng pin or not. to know more about the format of the device descriptor and the strings please refer to the usb 1.1 specifications. for information on the ufi inquiry data, please refer to the ?usb mass storage class ufi command specification?.
smsc ds ? usb97cfdc2-01 page 14 rev. 02-27-07 datasheet 7 board test mode operation by driving the ntesten pin low, the device will be placed into a special test mode to allow verification of attachment of the device to the circuit board. every pin except the tstout, xtal2, and the power and ground pins become an input to an xnor chain, as shown below, to allow continui ty to be tested on the board. this test should individually toggle the state of t he trace connected to the pin being examined for continuity, and the tstout pin monitored for toggle of state. if no toggle occurs, eit her the pin under test is discontinuous, or the tstout pin is not connected on the board pin1 pin2 pin3 pin100 tstout
smsc ds ? usb97cfdc2-01 page 15 rev. 02-27-07 datasheet 8 dc parameters maximum guaranteed ratings operating temper ature ra nge.................................................................................................... ....................... 0 o c to +70 o c storage temper ature range ...................................................................................................... ......................-55 o to +150 o c lead temperature range (sol dering, 10 seconds ) ................................................................................. .................... +325 o c positive voltage on any pin, wi th respect to ground (not e 1) ................................................................... ................ v cc +0.3v negative voltage on any pin, with respect to gr ound............................................................................ ..........................-0.3v maximum v cc ............................................................................................................................... ....................................+3.6v note 1: maximum voltage on all i type inputs and the is inputs, od 12 and od24 outputs for floppy disk drive interface is 5.25v *stresses above the specified par ameters could cause permanent damage to the dev ice. this is a stress rating only and functional operation of the dev ice at any other condition above those indica ted in the operation sections of this specification is not implied. note 2: when powering this device from laborat ory or system power supplies, it is important that the absolute maximum ratings not be exceeded or device failure can result. some power supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, volt age transients on the ac power line may appear on the dc output. when this possibility exists, it is s uggested that a clamp circuit be used. dc electrical characteristics (t a = 0c - 70c, v cc = +3.3 v 10%) parameter symbol min typ max units comments i type input buffer low input level high input level v ili v ihi 2.0 0.8 v v ttl levels iclk input buffer low input level high input level v ilck v ihck 2.2 0.4 v v input leakage (all i and is buffers) low input leakage high input leakage i il i ih -10 -10 +10 +10 ua ua v in = 0 v in = v cc o8 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v ua i ol = 8 ma i oh = -4 ma v in = 0 to v cc (note 1) i/o8(p) type buffer low output level high output level output leakage io8 io8p v ol v oh i ol i ol 2.4 -10 -50 0.4 +10 +10 v v a a iol = 8ma ioh = -4ma vin = 0 to vcc (note 1) vin = 0 to vcc (note 1)
smsc ds ? usb97cfdc2-01 page 16 rev. 02-27-07 datasheet parameter symbol min typ max units comments od12 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a iol = 12ma vin = 0 to vcc (note 1) o24 type buffer low output level high output level output leakage v ol v oh i ol 2.4 -10 0.4 +10 v v a iol = 24ma ioh = -12ma vin = 0 to vcc (note 1) od24 type buffer low output level output leakage v ol i ol -10 0.4 +10 v a iol = 24ma vin = 0 to vcc (note 1) io-u note 2 supply current active supply current standby i cc i csbu 30 120 75 250 ma a all outputs open. note 1: output leakage is measured with the current pins in high impedance. note 2: see appendix a for usb dc electrical characteristics. capacitance t a = 25c; fc = 1mhz; v cc = 3.3v limits parameter symbol min typ max unit test condition clock input capacitance c in 20 pf input capacitance c in 10 pf output capacitance c out 20 pf all pins except usb pins (and pins under test tied to ac ground)
smsc ds ? usb97cfdc2-01 page 17 rev. 02-27-07 datasheet 9 ac parameters t2 t1 t2 clocki figure 1 - input clock timing table 2 ? input clock timing parameters name description min typ max units t1 clock cycle time for 14.318mhz 69.84 ns t2 clock high time/low time for 24mhz 41.9/ 27.9 27.9/ 41.9 ns t r , t f clock rise time/fall time (not shown) 5 ns fa[0:19 ] fd[7:0 nfrd nfwr t1 t5 t3 t4 t2 figure 2 ? flash read timing table 3 ? flash read timing name parameter min typ max units t1 fa[14:0] address setup time to nfrd asserted 40 ns t2 nfrd pulse width 110 ns t3 fd[7:0] data se tup time to nfrd de-asserted 30 ns t4 fd[7:0] data hold time from nfrd de-asserted 0 ns t5 fa[14:0] address hold time from nfrd de-asserted 35 ns
smsc ds ? usb97cfdc2-01 page 18 rev. 02-27-07 datasheet figure 3 - disk drive timing typ t3 t1 t2 t4 t5 t6 t7 t8 ndir nstep nds0 nindex nrdata nwdata *x specifies one mclk period and y specifies one wclk period. mclk = 16x data rate (at 500 kbp/s mclk = 8 mhz) wclk = 2x data rate (at 500 kbp/s wclk = 1 mhz) parameter min max units t1 t2 t3 t4 t5 t6 t7 t8 ndir set up to nstep low nstep active time low ndir hold time after nstep nstep cycle time nds0-1 hold time from nstep low nindex pulse width nrdata active time low nwdata write data width low x* x* x* x* x* x* ns y* 4 24 96 132 20 2 40 .5 name
smsc ds ? usb97cfdc2-01 page 19 rev. 02-27-07 datasheet 10 usb parameters the following tables and diagrams were obtained from the u sb specification 10.1 usb dc parameters 0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 common mode input voltage (volts) minimum differential sensitivity (volts) figure 4 - differential input sensitivi ty over entire common mode range table 4 - dc electrical characteristics parameter symbol conditions (note 1, 2) min typ max unit supply voltage powered (host or hub) port vbus 4.4 5.25 v supply current function icc note 4 100 ma un-configured function (in) iccinit note 5 100 ua suspend device iccs 100 ua leakage current hi-z state data line leakage ilo 0 v < vin < 3.3 v -10 10 ua input levels differential input sensitivity vdi |(d+) - (d-)|, and figure 4 0.2 v differential common mode range vcm includes vdi range 0.8 2.5 v single ended receiver threshold vse 0.8 2.0 v output levels static output low vol rl of 1.5 k to 3.6 v 0.3 (3) v static output high voh rl of 15 k to gnd 2.8 3.6 (3) v capacitance
smsc ds ? usb97cfdc2-01 page 20 rev. 02-27-07 datasheet parameter symbol conditions (note 1, 2) min typ max unit transceiver capacitance cin pin to gnd 20 pf terminals bus pull-up resistor on root port rpu (1.5 k +/- 5%) 1.425 1.575 k bus pull-down resistor on downstream port rpd (15 k +/- 5%) 14.25 15.75 k note 1: all voltages are measured from the local ground potential, unless ot herwise specified. note 2: all timing use a capacitive load (cl) to ground of 50pf, unless otherwise specified. note 3: this is relative to vusbin. note 4: this is dependent on block configuration set by software. note 5: when the internal ring oscillator and waiting for first setup packet.
smsc ds ? usb97cfdc2-01 page 21 rev. 02-27-07 datasheet 10.2 usb ac parameters full speed: 4 to 20ns at c l = 50pf differential data lines 10% rise time 90% fall time t f t r 10% 90% c l c l figure 5 - data signal rise and fall time t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 figure 6 - differential data jitter t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop figure 7 - differential to eop transition skew and eop width
smsc ds ? usb97cfdc2-01 page 22 rev. 02-27-07 datasheet differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 figure 8 - receiver jitter tolerance table 5 - full speed (12mbps) source electrical characteristics parameter sym conditions (note 1, 2, 3) min typ max unit driver characteristics transition time: rise time fall time tr tf note 4,5 and figure 5 cl = 50 pf cl = 50 pf 4 4 20 20 ns ns rise/fall time matching trfm (tr/tf) 90 110 % output signal crossover voltage vcrs 1.3 2.0 v drive output resistance zdrv steady state drive 28 43 data source timing full speed data rate tdrate ave. bit rate (12 mb/s +/- 0.25%) note 8 11.95 12.03 mbs frame interval tframe 1.0 ms +/- 0.05% 0.999 5 1.0005 ms source differential driver jitter to next transition for paired transitions tdj1 tdj2 note 6, 7 and figure 6 -3.5 -4.0 3.5 4.0 ns ns source eop width teopt note 7 and figure 7 160 175 ns differential to eop transition skew tdeop note 7 and figure 7 -2 5 ns receiver data jitter tolerance to next transition for paired transitions tjr1 tjr2 note 7 and figure 8 -18.5 -9 18.5 9.0 ns ns eop width at receiver must reject as eop must accept teopr1 teopr2 note 7 and figure 7 40 82 ns ns
smsc ds ? usb97cfdc2-01 page 23 rev. 02-27-07 datasheet parameter sym conditions (note 1, 2, 3) min typ max unit cable impedance and timing cable impedance (full speed) zo (45 +/- 15%) 38.75 51.75 cable delay (one way) tcbl 30 ns note 1: all voltages are measured from the local ground potential, unless ot herwise specified. note 2: all timing use a capacitive load (cl) to ground of 50pf, unless otherwise specified. note 3: full speed timings have a 1.5k pull-up to 2.8 v on the d+ data line. note 4: measured from 10% to 90% of the data signals. note 5: the rising and falling edges should be smoothly transiting (monotonic). note 6: timing differences between t he differential data signals. note 7: measured at crossover point of differential data signals. note 8: these are relative to the 14.318 mhz crystal.
smsc ds ? usb97cfdc2-01 page 24 rev. 02-27-07 datasheet 11 mechanical outline figure 9 - 100 pin tqfp package min nominal max remar k a ~ ~ 1.60 overall package height a1 0.05 ~ 0.15 standoff a2 1.35 1.40 1.45 body thickness d 13.80 14.00 14.20 x span d/2 6.90 7.00 7.10 1 / 2 x span measure from centerline d1 11.80 12.00 12.20 x body size e 13.80 14.00 14.20 y span e/2 6.90 7.00 7.10 1 / 2 y span measure from centerline e1 11.80 12.00 12.20 y body size h 0.09 ~ 0.20 lead frame thickness l 0.45 0.60 0.75 lead foot length from centerline l1 ~ 1.00 ~ lead length e 0.40 basic lead pitch 0 o 3.5 o 7 o lead foot angle w 0.13 0.16 0.23 lead width r1 0.08 ~ ~ lead shoulder radius r2 0.08 ~ 0.20 lead foot radius ccc ~ ~ 0.08 coplanarity note 1: controlling unit: millimeter note 2: minimum space between protrusion and an adjacent lead is .007 mm. note 3: package body dimensions d1 and e1 do not include the mold protrusion. maximum mold protrusion is 0.25 mm note 5: details of pin 1 identifier are optional but mu st be located within the zone indicated.

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